/******************************************************************************
*
*    File Name:  DDRModule.sv
*      Version:  1.0
*         Date:  June 13th, 2013
*        Model:  
*    Simulator:  Questa Sim- Mentor Graphics (Version 64 10.2a)
*
* Dependencies:  DDRInterface.sv, DDRStub.sv
*
*       Author:  Nachiket Khasbag & Nikhil Patil 
*        Email:  nachiket@pdx.edu, pnikhil@gmail.com
*        Phone:  404-660-0757, 971-300-1728
*   University:  Portland State University
*
*  Description:	 To connect to controller side module.
*
*
******************************************************************************/


`include "DDRInterface.sv"
//import DDRStub::*;
timeunit 10ns;

module top_level(input logic Clock);
  DDRInterface DDR(.Clock(Clock));  
  Controller C1(.DDR(DDR), .Clock(Clock));
endmodule



module Controller(DDRInterface DDR,
                  input logic Clock);
    
  always @(posedge Clock)
  begin
    
    /*********************** INSERT YOUR CODE HERE *********************/
    
    // FOR EG. READ(), WRITE(), INIT()
     
    // ON A READ COMMAND, THE SIGNAL data_read GOES LOW.
    // WHEN data_read IS HIGH, IT INDICATES DATA WILL START 
    // TO APPEAR IN BURSTS OF 8 BITS FROM THE NEXT POSITIVE 
    // CLOCK EDGE
    // YOU HAVE TO WAIT TILL data_read GOES LOW
    
    // ON A WRITE COMMAND, THE SIGNAL data_write GOES LOW.
    // WHEN data_write IS HIGH, IT INDICATES DATA HAS BEEN WRITTEN 
    // TO THE DDR
    // YOU HAVE TO WAIT TILL data_write GOES LOW 
    
    // PLEASE HAVE A LOOK AT THE TESTBENCH
    
  end
  
endmodule